1. Field of the Invention
The present invention relates to a data processing apparatus and method for swapping data values.
2. Description of the Prior Art
Two types of data formats are commonly supported within the computing industry, namely big-endian and little-endian. In little-endian format, an address for a data word always identifies the least significant byte of the addressed data word, and hence in little-endian notation byte [0] is used to denote the least significant byte of the data word. In big-endian format, the address for a data word always identifies the most significant byte of the addressed data word, and accordingly byte [0] is used in big-endian notation to identify the most significant byte of the data word.
Typically, the data processing unit of a data processing apparatus will be arranged to apply operations to data of one particular format, and hence one data processing unit may be arranged to operate on big-endian data words, whilst another data processing unit may be arranged to operate on little-endian data words. However, there is an increasing need for information to be shared between data processing units, and accordingly steps need to be taken to ensure that any particular processor can handle data that has originated as either big-endian data or little-endian data. As an example, within large data processing systems, different types of computers are now being purchased to perform different tasks, and accordingly the overall system may include both big-endian processors and little-endian processors, with the data needing to be shared between the various processors.
One way in which this problem has been dealt with in the prior art is for a chip containing a particular processor (for example a little-endian processor) to be arranged so that only data of the appropriate format (in this example little-endian data) can be received at the interface to the chip. This has the advantage that it avoids increased complexity within the chip to facilitate handling of both big-endian and little-endian data. However, the main disadvantage is that such an approach places significant constraints on the logic arranged to interface with the chip, since functionality needs to be put in place to enable the endianness of data to be swapped where necessary prior to input of that data to the chip.
A data word can be considered as consisting of a plurality of data values, where a data value is the basic unit of addressable data. Hence, typically, a data value will be a byte of data, and the data word will consist of a plurality of bytes, e.g. four bytes for a 32-bit data word, eight bytes for a 64 bit data word, etc. When swapping the endianness of a data word, the ordering of the constituent data values (e.g. bytes) is reversed. Hence, if a big-endian 32-bit data word consists of the bytes ABCD, then the swapping of the endianness of that data word will result in the equivalent little-endian data word DCBA.
With the above described prior art approach, where any required switching of endianness occurs prior to input of the data to the chip containing the data processing unit, the size of the data word subjected to the endianness swap is dictated by the bandwidth of the interface. Hence, if the interface has a bandwidth of 32-bits, the data word will be considered to be 32-bits in length, and any endianness swap will involve the above-described reversal of the four bytes making up the 32-bit data word. Similarly, if the interface has a bandwidth of 64-bits, then the data word will be considered to be 64-bits in length, and an endianness swap operation external to the chip will involve reversal of the order of the eight bytes making up that data word.
This approach hence does adversely affect the ability of the data processing unit on the chip to handle different types of data structures (for example data word, half data word, unaligned data word (i.e. a data word where the address is not a multiple of the data word size), etc), in situations where a swap in endianness of the data is required prior to inputting that data into the chip.
An alternative approach to that described above is to allow data of either endianness to be input via the interfaces of the chip, and then provide some internal functionality to swap the endianness of the data if required prior to it being processed by the data processing unit. However, due to the extra complexity resulting from the presence of data of either endianness on the same chip, it has up to now been considered possible to only provide an endianness swapping functionality for a predetermined size data word. Hence, although this approach alleviates the constraint that would otherwise be placed on logic designed to interface with the chip if the chip were only to be able to receive data of one endianness, the problem of efficiently handling other types of data structures, such as sub-words (for example halfwords), remains.
Accordingly, it is an object of the present invention to provide a data processing apparatus which can receive both little-endian and big-endian data but which can efficiently handle data structures other than one predetermined size data word.